DFT Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will be responsible for DFT implementation using industry standard tools for high-speed CPU core design. This role is remote based out of the United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are You have a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or Computer Science, along with 10+ years of relevant DFT experience. You have hands-on experience with industry-standard DFT tools such as Synopsys and Siemens, as well as scripting in TCL and Python. You bring expertise in DFT planning, SoC-level silicon debug, formal verification, and signoff of inserted DFT logic. You are a strong cross-functional collaborator who can assess risk, communicate resource needs, and deliver in a complex technical environment. What we need Build and execute chip-level DFT strategies for high-speed CPU core designs and multi-chiplet System-in-Package programs. Implement and verify DFT features including scan chains, memory BIST, and JTAG to support manufacturing test and silicon debug. Partner with RTL, physical design, and verification teams to ensure testability throughout the design flow. Script, automate, and analyze DFT flows using industry-standard EDA tools, including ATPG and fault coverage reporting. What you will learn How to develop DFT strategies for advanced multi-chiplet and System-in-Package designs.