RISC-V AI / HPC & Agentic Software Engineering Lead

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is building next-generation RISC-V CPUs optimized for AI, high-performance computing, and emerging autonomous AI systems. As the RISC-V AI / HPC & Agentic Software Engineering Lead, you will operate at the hardware–software boundary, enabling AI, HPC, and agentic AI software stacks on Tenstorrent’s RISC-V processors. This role is responsible for integrating and optimizing Tenstorrent’s LLK (Low-Level Kernel) infrastructure for CPU execution, while leading the bring-up of a RISC-V-native agentic AI software stack — including runtime orchestration, distributed execution frameworks, memory systems, and developer tools required for goal-driven AI systems. You will work closely with CPU architects, microarchitecture teams, compiler engineers, and AI kernel developers to ensure tight alignment between software capabilities and RISC-V architectural features. This role is remote, based out of North America. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A systems-oriented software engineer with deep experience in HPC and AI software stacks. Experienced with distributed AI systems, orchestration frameworks, or agentic AI architectures. Comfortable working close to hardware and instruction-level programming. Skilled at translating performance targets into architectural and software requirements. Experienced in runtime systems, profiling, and low-level optimization. Motivated by hardware–software co-design and scaling next-generation AI infrastructure. What We Need Strong background in HPC and AI software development. Solid understanding of RISC-V architecture (ISA, extensions, micro-architectural implications). Proficiency in C/C++ and systems programming. Experience optimizing performance-critical code paths.